Custom IC design automation
My research starts from custom IC design, connecting circuit intent, layout constraints, and implementation-aware automation for practical chip design flows.
Ph.D. Candidate, Peking University
Haoyi Zhang
I work on custom IC design automation, including standard-cell automation, CIM circuits and DSE, AI4EDA, and practical analog design automation.
20+
Publications
1
DATE Best Paper Award
4
Research internships
EDA
Custom IC, Cell, CIM, AI4EDA
Visitor Map
Global visitor map
A lightweight world-map view that stays consistent with the homepage. Open the live stats page for the real shared visitor-dot map.
Visitor overview
This homepage view uses the custom styled map. The external live stats page shows the real city-level visitor dots from the shared service.
Site visits
View the full live visitor map
Research
Custom IC design automation
From standard cells and CIM/DSE to AI4EDA and analog design automation.
CIM circuits and DSE
Computing-in-memory circuit design, automatic CIM compiler flows, and design space exploration across precision, architecture, and circuit tradeoffs.
AI4EDA
Large language models, multi-agent systems, and learning-based design intent modeling for more interactive and generalizable EDA tools.
Standard cell automation
Standard-cell layout synthesis, multi-row cell generation, and layout/netlist-aware PPA prediction for scalable cell library design.
Analog design automation
Analog layout generation, migration, routing, placement, sizing, and human-in-the-loop editing for analog and mixed-signal circuits.
Selected Work
Publications
Conference Publications
- FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction. International Conference on Machine Learning (ICML), Seoul, South Korea, 2026. [PDF]
- PowerCube: A Formula-in-the-Loop Framework for Cross-Stage Power Map Prediction. International Symposium of Electronics Design Automation (ISEDA), Singapore, 2026. [PDF]
- GRAIN: A Design-Intent-Driven Analog Layout Migration Framework. International Symposium of Electronics Design Automation (ISEDA), Singapore, 2026. [PDF]
- PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation. Design Automation Conference (DAC), Long Beach, USA, 2026, invited paper. [PDF]
- EPiCell: ElectroPhysical CoModeling for Standard Cell PPA Prediction. Design Automation Conference (DAC), Long Beach, USA, 2026. [PDF]
- GRAIN: A Design-Intent-Driven Analog Layout Migration Framework. Design, Automation & Test in Europe Conference (DATE), Verona, Italy, 2026. [PDF]
- MOSTAR: Multi-Stage Hierarchical Bayesian Optimization for Substructure-Aware High-Dimensional Analog Circuit Sizing. Asia and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, China, 2026, co-first-author. [PDF]
- SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. Design, Automation & Test in Europe Conference (DATE), Lyon, France, 2025, co-first-author. [PDF]
- AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models. International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025. [PDF]
- LayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction. IEEE International Symposium on Circuits and Systems (ISCAS), London, UK, 2025. [PDF]
- Multi-Row Standard Cell Layout Synthesis with Enhanced Scalability. International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025. [PDF]
- SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. Design, Automation & Test in Europe Conference (DATE), Valencia, Spain, 2024. [PDF]
- Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Newark, USA, 2024. [PDF]
- EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. Design Automation Conference (DAC), San Francisco, USA, 2024. [PDF]
- SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. Design, Automation & Test in Europe Conference (DATE), Antwerp, Belgium, 2023. Best Paper Award. [PDF]
- Multi-Scenario Analog and Mixed-Signal Circuit Routing with Agile Human Interaction. International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, 2023. [PDF]
- A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. IEEE Custom Integrated Circuits Conference (CICC), San Antonio, USA, 2023. [PDF]
- Intelligent and Interactive Analog Layout Design Automation. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Nanjing, China, 2022. [PDF]
Journal Publications
- LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025, co-first-author. [PDF]
- The dawn of AI-native EDA: Promises and challenges of large circuit models. Science China Information Sciences, 2024. [PDF]
- Post-Layout Simulation Driven Analog Circuit Sizing. Science China Information Sciences, 2024. [PDF]
- A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function with < 6×10-9 Bit Error Rate Through Efficient Redundancy Strategy. IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2024. [PDF]
- A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. IEEE Journal of Solid-State Circuits (JSSC), 2023. [PDF]
- Interactive Analog Layout Editing with Instant Placement and Routing Legalization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022, co-first-author. [PDF]
Background
Education
Peking University
Ph.D. Candidate, Integrated Circuits
Beihang University
Bachelor, Microelectronics
Recognition
Awards
- Design, Automation & Test in Europe Conference (DATE) Best Paper Award, first author, 2023
- National Scholarship, Peking University, 2024
- Merit Student, Peking University, 2024
- Industry Contribution Award, Department of Design Automation and Computing Systems, Peking University, 2023
- Outstanding Research Award, Peking University, 2023
- First Prize, Huawei Scholarship, 2023
- Third Prize, Huawei Scholarship, 2022
- Outstanding Graduate, Beihang University, 2022
- First Prize Scholarship (8%), Beihang University, 2021
- Merit Student, Beihang University, 2021
- Second Prize, EDA Elite Design Challenge, 2021 and 2022
- Empyrean Enterprise Special Award, EDA Elite Design Challenge, 2021
Academic Service
Review Service
ICML Silver Reviewer
Recognized as a Silver Reviewer for the International Conference on Machine Learning (ICML 2026).
Journals and conferences
Reviewed for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ACM Transactions on Design Automation of Electronic Systems (TODAES), IEEE Transactions on Circuits and Systems I (TCAS-I), Design Automation Conference (DAC), IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Design, Automation & Test in Europe Conference (DATE), and related EDA and circuit-design venues.
Experience
Internships
ByteDance - Jindouyun Program
Physical Design Intern, Beijing
Microsoft Research Asia
Research Intern, Machine Learning Group, Beijing
Huawei Technologies Co., Ltd. (HiSilicon-Turing)
Development Intern, Shanghai
Primarius Technology Co., Ltd.
Development Intern, Beijing
Get in touch